1. Field of the Invention
The present invention relates generally to data storage devices, and more specifically to dual media storage devices.
2. Description of the Related Art
General-purpose computers require a mass storage system. Unlike main memory, which is used for the direct manipulation of data, mass storage is used to retain data. Generally a program is stored in mass storage and, when the program is executed, either the entire program or portions of the program are copied into main memory. The speed at which a system is able to locate and transfer the program and its associated data from the mass storage device into the main memory is integral to the overall speed of a system.
Common mass storage devices include floppy disks, hard disks, optical discs and tapes. Each device has both strengths and weaknesses, which can relate to capacity, price, speed and portability.
Additionally, other devices, such as flash memory, can provide non-volatile storage. Flash memory is a type of electrically erasable programmable read-only memory (EEPROM). Although flash memory is typically not as fast as the volatile main memory, it is faster than hard disks.
The inventor has previously explored the concept of merging separate devices into a single mass storage system in order to maximize each device's strengths and minimize each device's weaknesses. For example, the inventor was also identified as the inventor for PCT application “Memory Device” WO 97/50035 that was published on Dec. 31, 1997, incorporated herein by reference for all purposes. That PCT application described a memory system that included both a relatively slow-access mass data storage device, such as a hard disk, and a relatively fast-access data storage device, such as flash memory. A similar concept has been explored in the U.S. patent, “Mass Computer Storage System Having Both Solid State and Rotating Disk Types of Memory,” U.S. Pat. No. 6,016,530, issued to Daniel Auclair and Eliyahou Harari on Jan. 18, 2000, incorporated herein by reference in its entirety for all purposes.
By combining a non-volatile flash memory device with a non-volatile hard disk, a resulting mass storage system can be greater than the sum of its parts. However, such memory system was specifically limited to a situation where only one version of each data sector was ever maintained. The data sector was stored in either the high-speed memory or in the slow-access mass data storage device, making the logical address space equal to the sum of the capacities of the high-speed memory and the slow-access mass storage device.
There are many commercially successful non-volatile memory products being used today that employ an array of flash cells formed on one or more integrated circuits chips. A memory controller, usually (but not necessarily) on a separate integrated circuit chip, controls operation of the memory array. Such a controller typically includes a microprocessor, some non-volatile read-only memory (ROM), a volatile random-access memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as it passes through the controller during programming and reading operations.
Memory cells of a typical flash array are divided into discrete blocks of cells that are erased together. That is, the erase block is the erase unit—a minimum number of cells that are simultaneously erasable. Each erase block typically stores one or more pages of data, the page programmed or read in parallel in different sub-arrays or planes. Each planes typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives. Such memories are typically configured with 16, 32 or more pages within each erase black, and each page stores one or just a few host sectors of data.
In order to increase the degree of parallelism during programming and reading operations the array is typically divided into sub-arrays, commonly referred to as planes. Each plane can contain its own data registers and other circuits to allow parallel operation such that the sectors of data may be programmed to or read from all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. No. 5,798,968, “Plane decode/virtual sector architecture,” issued to Lee et al. on Aug. 25, 1998, and U.S. Pat. No. 5,890,192, “Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM,” issued to Lee et al. on Mar. 30, 1999, both of which incorporated herein by reference in their entireties for all purposes.
To further efficiently manage the memory, erase blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one erase block from each plane. Use of the metablock is described in international patent application “Partial Block Data Programming And Reading Operations In A Non-Volatile Memory,” publication no.: WO02/058074 on Jul. 25, 2002, incorporated herein by reference in its entirety for all purposes. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all erase blocks of a metablock are erased together. The controller in a memory system operated by such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address.
Flash memory systems of this type are commonly used as mass storage devices in portable applications. The flash memory device communicates with a host system via a logical interface using a protocol such as ATA, and is frequently in the form of a removable card. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication systems, and similar types of equipment. Besides the memory card implementation, this type of memory can alternatively be embedded into various types of host systems.
In the past, flash memory has been used for various data caching functions, for storage of a computer's BIOS, or as an extension of a mass storage device (as in the above PCT application). It has been used within a hard disk device for caching write or read data. For example, U.S. Pat. No. 5,586,291, “Disk controller with volatile and non-volatile cache memories,” to Lasker et al. on Dec. 17, 1996, incorporated herein by reference in its entirety for all purposes, describes the use of a non-volatile memory as a write cache for a hard disk, with data mirrored in a volatile memory that acts as a read cache. U.S. Pat. No. 5,636,355, “Disk cache management techniques using non-volatile storage,” to Ramakrishnan et al. on Jun. 3, 1997, and U.S. Pat. No. 5,542,066, “Destaging modified data blocks from cache memory,” to Mattson et al. on Jul. 30, 1996, both of which are incorporated herein by reference in their entireties for all purposes, also describe use on non-volatile memory as a write cache for a hard disk, and purging or destaging algorithms for moving data from the cache to the hard disk. In known applications of non-volatile memory as a disk cache, data identified by a logical address in the hard drive is temporarily mapped to a physical location in the non-volatile memory.
There are continuing efforts to improve mass storage devices.